What’s The Differences Between FPGA And CPLD ?

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FPGA/CPLD can complete the function of any digital device, from high-performance CPU to simple 74 circuits, all can be realized by FPGA/CPLD. FPGA/CPLD is like a blank piece of paper or a stack of wood, engineers can freely design a digital system through the traditional schematic input method or hardware description language.

Through software simulation, we can verify the correctness of the design in advance. After the PCB is completed, the online modification capability of the FPGA/CPLD can also be used to modify the design at any time without changing the hardware circuit.

What is the Differences Between FPGA And CPLD

Using FPGA/CPLD to develop digital circuits can greatly shorten the design time, reduce the PCB area, and improve the reliability of the system. FPGA/CPLD can also do the front-end verification of digital IC design, which can greatly reduce the cost of IC design.

These advantages of FPGA/CPLD made FPGA/CPLD technology develop rapidly after the 1990s, and also greatly promoted the progress of EDA software and hardware description language (HDL).

1. What’s the Differences Between FPGA And CPLD

A.There are differences in how manufacturers name their products

PLD (Programmable Logic Device) is a general term for programmable logic devices, an early multi-EEPROM process, based on a Product Term structure. FPGA (Field Programmable Gate Arry) refers to Field Programmable Gate Array, first invented by Xilinx Company. Most of them are SRAM processes, based on the look-up table (Look Up Table) structure, and EPROM for external configuration is required.

Xilinx calls the SRAM process and the PLD of the EPROM used for external configuration FPGA, the Flash process (similar to the EEPROM process), and the PLD of the product term structure is called CPLD;

Altera calls its own PLD products: MAX series (EEPROM process), FLEX/ACEX/APEX series (SRAM process) as CPLD, namely complex PLD (Complex PLD).

Since the FLEX/ACEX/APEX series are also SRAM technology, the EPROM used for external configuration is the same as the Xilinx FPGA, so many people call Altera’s FELX/ACEX/APEX series products also called FPGA.

2. The main difference in product structure

The granularity of logical blocks is different

Logic block refers to the functional modules divided by structure in the PLD chip. It has a relatively independent combinational logic array, and the blocks are connected by an interconnection system. The CLB in FPGA is a logic block, which is characterized by small granularity and input variables of 4 to 8 , the output is 1 to 2, so it is only a logic unit, and there are dozens to nearly a thousand such units in each chip.

The granularity of logic blocks in CPLD is relatively large, usually there are dozens of input terminals and one or twenty output terminals, and each chip is only divided into several blocks. Such a coarse block structure is not as flexible as an FPGA when used.

The interconnect structure between the logic is different

The interconnection of logic blocks of CPLD is lumped, which is characterized by equal delay, and the delay between any two blocks is equal. This structure brings great convenience to designers; the interconnection of FPGA is distributed. The delay is related to the layout of the system.

3. There are differences in the scope of application

Logic systems can generally be divided into two categories:


  1. Logic-intensive: such as cache control, DRAM control and DMA control, etc., they only require little data processing power, but the logic relationship is generally complex


  1. Data-intensive: Data-intensive requires a lot of data processing capabilities, and its applications are more common in the field of communications.


In order to choose a suitable PLD chip, it should be examined from the aspects of speed and performance, logic utilization, ease of use, programming technology, etc.

Speed and Performance

Data-intensive systems, such as two-dimensional convolvers that process signals in communications. In a logic system that implements this algorithm, each unit requires fewer inputs, but many such logic units are needed.

These requirements are consistent with the structure of FPGA. Because of the small granularity of FPGA, the transmission delay time from input to output is very short, so high unit speed can be obtained. Control-intensive systems are usually input-intensive, logic complex, CLB The input terminals of the CLB are often not enough, and multiple CLBs need to be cascaded in series.

At the same time, the connection between CLBs may pass through multi-level general-purpose PI or long lines, resulting in a sharp drop in speed. Therefore, the actual transmission delay time is larger than that of CPLD. For example, to implement a DRAM controller, it consists of four functional blocks: refresh state machine , refresh address counter, refresh timer and address selection switch, there are dozens of input terminals required, obviously CPLD is more suitable.

logical utilization

Logic utilization refers to the degree of utilization of resources in the device. CPLD has few logic registers, FPGA has weak logic and more registers, which corresponds to control-intensive systems and data-intensive systems. For example, the is2pLSI1032 with the same scale of 6000PLD gates has 192 registers; and XC4005E has 616 registers. Therefore, from the perspective of logic utilization, for the design of more complex combinational circuits, a coarser-grained CPLD should be used, and for a design with more flip-flops, a fine-grained FPGA should be used.

Ease of use

The ease of use must first consider the predictability of performance. In this regard, CPLD is better than FPGA. For CPLD, usually as long as the number of input and output ports, the number of internal gates and flip-flops does not exceed the resources of the chip and there is a certain margin, always It is achievable. For FPGA, it is difficult to predict, because the number of CLB logic levels required to complete the design cannot be determined in fact, and satisfactory results can only be obtained by many experiments.

the difference in programming technology

FPGA programming information is stored in external memory, and additional memory chip is required, which has poor confidentiality and data is easily lost after power failure. CPLD adopts the best E2CMOS technology.

Although FPGA and CPLD are both programmable ASIC devices and have many common features, due to the differences in structure of CPLD and FPGA, they have their own characteristics:

① CPLD is more suitable for completing various algorithms and combinational logic, while FPGA is more suitable for completing sequential logic. In other words, FPGA is more suitable for flip-flop-rich structure, while CPLD is more suitable for flip-flop-limited and product-rich structure.


②The continuous wiring structure of CPLD determines that its timing delay is uniform and predictable, while the segmented wiring structure of FPGA determines the unpredictability of its delay.


③ FPGA has more flexibility than CPLD in programming. CPLD is programmed by modifying the logic function with fixed interconnected circuits, while FPGA is programmed mainly by changing the wiring of the interconnected wiring; FPGA can be programmed under logic gates, while CPLD is programmed under logic blocks.


④FPGA has higher integration level than CPLD, and has more complex wiring structure and logic implementation.


⑤CPLD is more convenient to use than FPGA. The programming of CPLD adopts E2PROM or FASTFLASH technology, no external memory chip is required, and it is easy to use. And the programming information of FPGA needs to be stored in the external memory, the use method is complicated.


⑥ CPLD is faster than FPGA and has greater time predictability. This is because FPGA is gate-level programming, and distributed interconnection is used between CLBs, while CPLD is logic block-level programming, and the interconnection between its logic blocks is lumped.


⑦ In terms of programming, CPLD is mainly based on E2PROM or FLASH memory programming, and the programming times can reach 10,000 times. The advantage is that the programming information is not lost when the system is powered off. CPLD can be divided into two categories: programming on the programmer and programming on the system.

Most FPGAs are based on SRAM programming, and the programming information is lost when the system is powered off. Every time the system is powered on, the programming data needs to be rewritten into the SRAM from the outside of the device. The advantage is that it can be programmed any number of times, and can be programmed quickly during work, so as to achieve dynamic configuration at the board level and system level.


⑧CPLD has good confidentiality, while FPGA has poor confidentiality.


⑨ In general, the power consumption of CPLD is larger than that of FPGA, and the higher the integration, the more obvious it is.

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