FPGA Design Based on Various EDA Tools

Table of Contents

In today’s digital system design, the emergence of system-on-chip (SoC) technology has caused profound changes in the design field. In order to meet the requirement of product listing as soon as possible, the designer must reasonably choose the tool software provided by various EDA manufacturers to accelerate the design, so as to make the product develop soundly in this field. FPGA design is one of the important ways in the current digital system design field. Based on a variety of EDA manufacturers’ tools, this paper systematically introduces the process of FPGA design.

FPGA Design Based on Various EDA Tools

Digital logic division and FPGA internal structure

Digital Logical Tree Classification Diagram
Figure 1 shows a tree-like classification diagram of digital logic, from which it can be seen that Field Programmable Gate Array (FPGA) is an important branch of programmable logic devices in application-specific integrated circuits.

The internal resources of FPGA (taking Xilinx as an example) are generally divided into three parts: programmable logic block CLB, input and output block IOB and programmable connection PI. By programming and controlling PI to connect each CLB unit, a circuit with specific functions can be formed. Use the company’s special design software to design FPGA, and finally form a bit stream file controlled by PI to the CLB unit

The Virtex series FPGA products mainly promoted by Xilinx adopt 0.22 micron process and have the following features: support for 9 I/O standards, 4 delay-locked loops, coexistence of block storage and distributed storage, programmable pipeline delay storage, thermal control, configuration The rate is 500Mb/s.

And Altera’s Apex20ke series is also the company’s main FPGA product, which is different from Xilinx’s products in terms of internal wiring resources. In Virtex devices, it is divided into double long lines, single long lines and long lines, which can be selected according to the nearest principle when wiring; while in Apex20ke, the connection is only one kind of equal length, so it is more accurate in timing analysis.

FPGA design principles

FPGA design is roughly divided into six steps: design input, synthesis, functional simulation (pre-simulation), implementation, timing simulation (post-simulation), and configuration download. The design flow is shown in Figure 2. Each design step is described below.

FPGA Design Flowchart
FPGA Design Flowchart

Design input

Design input includes three ways of using hardware description language HDL, state diagram and schematic diagram. HDL design method is a good form for designing large-scale digital integrated circuits. In addition to VHDL and Verilog HDL in the IEEE standard, there are special languages ​​introduced by FPGA manufacturers, such as AHDL under Quartus.

The HDL language description is strong in terms of state machine, control logic, and bus functions, so that the circuit it describes can be better realized by specific hardware units under the action of a specific synthesizer (such as Synopsys’ FPGA Compiler II or FPGA Express). Schematic input has the characteristics of strong graphics, frugal units, and clear functions in terms of top-level design, data path logic, and manual optimization of circuits.

In addition, in the Quartus software environment of Altera Company, the Memory Editor can be used to directly edit the internal memory and place the data. The common method is mainly based on HDL language, supplemented by schematic diagrams, and mixed design is carried out to give full play to their respective characteristics.

Usually, the FPGA manufacturer’s software has an interface with the third-party software, which can import the third-party design files for processing. For example, both Quartus and FoundaTIon can use the EDIF netlist as the input netlist for direct placement and routing. After placement and routing, the generated corresponding files can be handed over to a third party for subsequent processing.

Design synthesis

Synthesis is to obtain a circuit design scheme that can meet the above requirements by optimizing the computer for a given circuit to realize the function and the constraints to realize the circuit, such as speed, power consumption, cost and circuit type.

That is to say, the file to be synthesized is an HDL file (or corresponding file, etc.), the basis of the synthesis is the description of the logic design and various constraints, and the result of the synthesis is a realization scheme of a hardware circuit, which must meet the expectations at the same time. functions and constraints.

For synthesis, there may be multiple schemes that meet the requirements, and the synthesizer will produce an optimal or near-optimal result. Therefore, the synthesis process is the optimization process of the design objective, and the final result is related to the performance of the synthesizer.

FPGA Compiler II is a complete tool for FPGA logic analysis, synthesis and optimization. It generates optimized netlist files from unoptimized netlists in HDL form, including three steps of analysis, synthesis and optimization.

Among them, analysis is to use Synopsys standard HDL syntax rules to analyze HDL source files and correct syntax errors; synthesis is to perform logic synthesis on HDL and FPGA netlist files with the target of selected FPGA structures and devices.

Optimization is to perform logic optimization on speed and area according to the user’s design constraints, and generate an optimized FPGA netlist file for use by FPGA placement and routing tools. can be driven by constraints.

When using FPGA Compiler II for design synthesis, the design source file should be imported under the current Project, and the syntax analysis should be performed automatically. Synthesize and optimize.

Here, the two steps can be carried out independently, and constraints are specified between the two steps, such as the determination of the clock, the delay of the channel and the port, the operator sharing of the module, the fan-out of the register and so on. If the design model is large, it can be synthesized in a hierarchical manner, first synthesizing lower-level modules, and then synthesizing upper-level modules.

When the upper-level module is synthesized, the lower-level module is set as Don’t Touch, which makes the design and synthesis process rational. The netlist formed after synthesis can be output in EDIF format, or in VHDL or Verilog HDL format, and import it into the special software provided by the FPGA design manufacturer that supports third-party design input, and then the subsequent FPGA chip can be implemented. . After the synthesis is completed, a report file can be output, listing the synthesis status and synthesis results, such as resource usage, post-synthesis level information, etc.

Simulation verification

Broadly speaking, design verification includes functional and timing simulation and circuit verification. Simulation refers to the complete testing of an implemented design using a design software package to simulate how it would work in an actual physical environment.

Pre-simulation refers to only testing and simulating the logic function to know whether the realized function meets the requirements of the original design. The simulation process does not add timing information and does not involve the hardware characteristics of specific devices, such as delay characteristics; , extracting the relevant timing parameters such as device delay, connection delay, and the simulation based on this is called post-simulation, which is a simulation that is close to the real device operation.

Design implementation

Realization can be understood as using the realization tool to map the logic to the resources of the target device structure, determine the optimal layout of the logic, select the routing channel connecting the logic and the input and output function blocks to connect, and generate corresponding files (such as configuration files and related files). Report). Usually can be divided into the following five steps:

(1) Conversion: Convert and merge multiple design files into one design library file.

(2) Mapping: Map the logic gates in the netlist to physical elements, that is, the process of dividing the logic design into configurable logic blocks, input and output blocks and other resources that constitute the programmable logic array.

(3) Placement and routing: Placement refers to taking the defined logic and input and output blocks from the map and assigning them to physical locations inside the FPGA, usually based on some advanced algorithm, such as minimum partitioning, simulated annealing and general Force direction relaxation, etc. to complete; routing refers to the use of automatic routing software to use routing resources to select paths and try to complete all logical connections. Because the latest design implementation tools are timing-driven, performing timing analysis on the entire signal path during placement and routing of the device, constraints can be used to manipulate the routing software to meet the performance requirements specified by the design. During the placement and routing process, timing information can be extracted simultaneously to form a report.

(4) Timing extraction: generate a back-mark file for subsequent timing simulation.

(5) Configuration: generate the bit stream file required for FPGA configuration.

Options can be set during implementation. Because it supports incremental design, it can repeat the routing multiple times, and each routing uses the previous routing information to make its routing better or achieve the design goal. In the implementation process, the download form of the default configuration should be set to make the subsequent bit stream download normal.

Timing Analysis

In the process of design implementation, timing analysis of the actual functional block delay and estimated routing delay of a design needs to be performed after mapping; Delay for static timing analysis.

To a certain extent, static timing analysis is arguably the most important step in the entire FPGA design. It allows the designer to analyze all critical paths in detail and generate an ordered report, and the report contains other debugging information, such as Fan-out or capacitive load of each network node, etc.

The static timing analyzer can be used to check the logic and timing of the design to calculate the performance of each path, identify possible traces, and detect the coordination of setup and hold times. The timing analyzer does not require the user to generate input stimuli or test vectors.

Although Xilinx and Altera have timing analysis tools on the FPGA development kit, when they have third-party specialized timing analysis tools, they only use the FPGA manufacturer’s design tools for placement and routing, and use third-party specialized timing analysis tools for timing analysis. Generally, FPGA manufacturers have interfaces with third-party timing analysis tools in their design environments.

PrimeTIme of Synopsys is a good timing analysis tool, which can be used to achieve better results. Save the synthesized netlist file in db format, which can be opened in PrimeTIme environment.

Use this software to check the timing of the critical path or the path that the designer is interested in, and analyze it, and then constrain the timing of the original design again, which can increase the working frequency or reduce the delay of the critical path. Similar to the synthesis process, static timing analysis is an iterative process that is closely tied to the place-and-route steps, which are usually performed multiple times until the timing constraints are well met.

In the process of synthesis and timing simulation, PrimeTIme is used interactively for timing analysis. After meeting the design requirements, the final physical verification of the FPGA chip can be carried out.

Download verification

Download is to download the bit stream formed after synthesis to a specific FPGA chip under the premise of correct function simulation and timing simulation, also called chip configuration. There are two configuration forms in FPGA design: directly configured by the computer through a dedicated download cable; automatically configured by the peripheral configuration chip when it is powered on.

Because FPGA has the property of losing power-down information, you can use the cable to download the bit stream directly in the early stage of verification, and then burn it into the configuration chip if necessary (such as Xilinx’s XC18V series, Altera’s EPC2 series).

There are many download methods when using cable to download. For example, for Xilinx’s FPGA download, you can use JTAG Programmer, Hardware Programmer, and PROM Programmer. For Altera’s FPGA, you can choose JTAG or Passive Serial. Because most FPGAs support the IEEE JTAG standard, using the JTAG port on the chip is a common download method.

After downloading the bit stream file to the inside of the FPGA device, the physical test of the actual device is the circuit verification. When the correct verification result is obtained, the correctness of the design is proved. Circuit verification is of great significance to FPGA production.

FPGA Design Based on Various EDA Tools

Figure 3 shows the flow chart of the simulation tool Modelsim cooperated with the synthesis tool FPGA Compiler II and the routing tool Foundation Series or Quartus to realize the FPGA design

Flowchart of implementing FPGA design using multiple EDA tools
Flowchart of implementing FPGA design using multiple EDA tools

In the design input stage, because Modelsim only supports VHDL or Verilog HDL, when choosing a variety of design input tools, you can use a text editor to complete the HDL language input, or you can use the corresponding tools to complete the input graphically, but you must be able to Export the corresponding VHDL or Verilog HDL format.

Graphical HDL design tools that have emerged in recent years can receive input methods such as logic structure diagrams, state transition diagrams, data flow diagrams, control flow diagrams, and truth tables, and convert these graphic formats into HDL texts through a configured translator. For example, Mentor Graphics’ Renoir and Xilinx’s Foundation Series have design tools that translate state transition diagrams into HDL texts. In this respect, the graphical interface of Summit (now merged into Innoveda) is more friendly and can export the corresponding HDL format.

It can be seen from Figure 3 that there are three places that can be simulated by Modelsim: the first is the register transfer level (RTL) simulation, which verifies the syntax and basic functions of the design (without timing information); the second It is a simulation for a specific FPGA manufacturer’s technology. This level of simulation is a functional-level simulation after synthesis and before implementation. The functional-level simulation generally verifies whether the correct function required by the designer can be obtained after synthesis; the third simulation is Gate-level simulation, this level of simulation is a simulation for gate-level timing, and gate-level simulation reflects the actual delay caused by layout and routing.

During the RTL simulation phase, a test bench should be built. This testbench enables simulation verification (RTL level, functional level, timing gate level) throughout the entire FPGA flow. The test bench not only provides test stimulus and receives response information, but also can test the key functions in the HDL simulation process (such as the correctness of the output value of the operation components, etc.). The generation of the test bench can be directly obtained by text editing, or input by graphical tools, and then translated into HDL format by the software. format obtained.

In the functional level simulation stage, it is generally verified whether the results of the synthesis are still the same as the RTL level simulation results.

In the gate-level simulation stage, since the function-level simulation has been carried out for the specific FPGA manufacturer’s technology, the timing information in the standard delay format can be obtained through the layout and routing for gate-level simulation.

Modelsim of Mentor Graphics is the best simulation tool in the industry. It has powerful simulation functions, friendly graphical interface, and windows such as structure, signal, waveform, process, and data flow. The FPGA design (in the form of HDL) is input and compiled to perform pre-simulation. The latest version of Modelsim SE/Plus 5.5 supports mixed simulation of VHDL and Verilog HDL. You can write HDL stimulus files or execute group mode mode during simulation.

The group mode is similar to the batch mode, which can continuously execute multiple execution commands written in the file in advance, which is particularly effective for re-simulation or repeated execution of multiple commands. Performance analysis and code coverage analysis can be performed during simulation. Performance analysis can analyze the percentage of the overall execution time occupied by each part of the code during the execution of the program code. With this information, designers can find design bottlenecks and reduce simulation time by optimizing code. Code coverage analysis can make the designer know exactly where the code is on the test bench, so as to facilitate the designer to debug.

To simulate by Modelsim, you need to export VHDL or Verilog HDL netlist. This netlist is composed of basic cells for a specific FPGA device. These basic units contain their definitions and characteristics in the manufacturer’s library provided by the FPGA manufacturer, and the manufacturer generally provides the VHDL or Verilog HDL library of their functions. Therefore, to simulate under Modelsim, it is necessary to set the manufacturer library information. If you use the Apex20ke series of Altera Corporation, you need to set or compile the Apex20ke_atoms.v (or .vhd) and Apex20ke_component.v files into the corresponding library of the project. In addition to the netlist, the standard delay file (sdf) of the layout and routing output is also required. Adding the sdf file to the simulation can be set and added in the window interface, or specified by excitation. For example, when using Verilog HDL, add the back-labeled statement $sdf_annotate(“ ”,Top) and specify it through the parameter path.

In the synthesis stage, the RTL-level design functions should be implemented and optimized into basic devices with equal functions and cell delays (but without timing information), such as flip-flops, logic gates, etc., using the constraint file specified by the designer, and the result The result is a functionally independent FPGA netlist. It does not contain timing information and can be used for subsequent placement and routing. The EDIF netlist can be exported after synthesis using FPGA Compiler II.

In the implementation stage, the EDIF netlist generated after synthesis is mainly used and the layout and routing are carried out based on the basic devices in the FPGA. You can use the routing tool Foundation Series to select specific devices (such as Virtex series devices) for placement and routing. You can also use the routing tool Quartus to select Apex20ke series devices for placement and routing. simulation below.

In today’s digital system design, using a variety of EDA tools for processing, and using FPGA to quickly design a dedicated system or as a verification method has become an indispensable way in digital system design. Understanding and being familiar with its design process should be an important part of today’s electronic system. A must-have for engineers.

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