What is FPGA Reconfigurable Technology ?

The FPGA reconfigurable technology is to load different Bitstream files during the operation of the FPGA through the control of the host computer. The FPGA chip reconfigures all or part of the internal resources according to different logics in the file to achieve the goal of dynamic switching of various functional tasks. This increases the flexibility of developing with FPGAs.

The PGA chip itself has the feature that it can be repeatedly erased and rewritten, allowing FPGA developers to write different codes for repeated programming, and the FPGA reconfigurable technology is based on this feature. Bitstream files use various logic resources inside the FPGA chip, so that the same logic circuit loads different functional modules in different time periods.

From the perspective of the time axis, each task function of the system is executed sequentially on the FPGA chip, and the overall functions of the system are fully realized. From a local point of view, the FPGA only performs a small task, while from the overall point of view, the FPGA completes the entire system task. Using one FPGA chip to complete the task that requires multiple FPGA chips, it can be seen that the utilization rate of the internal resources of the FPGA has been greatly improved.

The reconfigurable technology on the FPGA can be divided into two types according to the different structures inside the FPGA chip, namely dynamic reconfigurable and static reconfigurable. If the FPGA chip is a conventional SRAM structure, it can only be statically reconfigurable. The reconfiguration process must first send an interrupt command to stop the running program, and then load a new Bitstream file onto the FPGA.

If the FPGA chip is a special structure, it can be dynamically reconfigured. The reconfiguration process can be performed during the FPGA running period. The dynamic reconfiguration can not only change the module parameters at any time during the system running period, but also The reconfigurable area inside the FPGA dynamically reconfigures the circuit logic.

The dynamic reconfiguration of FPGA can be further divided into dynamic global reconfiguration and dynamic local reconfiguration. Dynamic global reconfiguration means that the host computer loads a new configuration file for the FPGA chip, and this configuration file contains all the resources in the entire FPGA that are involved in the new task requirements, so as to realize the FPGA reconfiguration. All logic circuits will be eliminated. Before the reconstruction operation is performed, a plurality of configuration files with different task requirements are loaded into the external memory first, and each configuration file contains all the logic resources of the FPGA chip involved in the task.

It is precisely because each configuration file contains all the resources of the entire FPGA chip, so the dynamic global reconfiguration can only select one configuration file from the external memory and load it into the FPGA chip. When the task corresponding to this configuration file ends, another new configuration file is selected to be loaded into the FPGA chip, and the switching of system function tasks is realized through the time-sharing loading of different configuration files.

This dynamic global reconfigurable implementation method is relatively easy. It only needs to write all the FPGA resources contained in the functional task in the configuration file. However, this implementation method contains all the resources, resulting in a large file and the configuration time. lengthen accordingly. Especially when the configuration files with similar logic circuits corresponding to two functional tasks are reconstructed successively, it is possible to change only the logic circuits with the difference, but all the resources inside the FPGA chip must be changed again.

Compared with dynamic global reconfigurability, dynamic local reconfigurability has greater flexibility. It only needs to generate a configuration file for the part of the logic function that is different between the two functional requirements, and load it into the specified reconfigurable area in the FPGA for reconfiguration, while the logic circuit in the specified static area in the FPGA does not need to occur. Change.

Suppose a system needs to switch two functions successively, and these two functions need to use 4 configuration files. Among them, function 1 needs to use configuration file 1, configuration file 2 and configuration file 3, and function 2 needs to use configuration file 1 and configuration file 4. Since configuration file 1 is required in both function 1 and function 2, first load configuration file 1 required by both functions into the static area of ​​the FPGA, and then load configuration file 2 and configuration file 3 in the reconfigurable area.

After function 1 runs, switch to function 2. Since configuration file 1 is still required in function 2, only the configuration file 2 and configuration file 3 that were previously loaded into the FPGA reconfigurable area only need to be loaded in the dynamic local reconfigurable area. The logic circuit is eliminated, and the operation of function 2 can be completed by reloading the configuration file 4 to generate the corresponding logic circuit. During the process of switching between the two functions, the static area where the configuration file 1 is located does not change.

Dynamic local refactoring only refactors part of the area, so the refactoring content in the configuration file is correspondingly smaller, and the refactoring time is also shortened. However, the difficulty of dynamic local reconfiguration lies in whether the size division of the static area and the reconfigurable area can meet the functional requirements of the system, how to communicate between the modules in the two areas, and how to make a reasonable layout in the reconfigurable area. wiring. Therefore, the implementation process using dynamic local reconfigurability is relatively complicated.

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